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Commit be5d40e5 authored by Whitney Armstrong's avatar Whitney Armstrong
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Initial commit 

Changes to be committed:
	new file:   Makefile
	new file:   fpga_io.c
	new file:   fpga_io.h
	new file:   maroc_io.c
	new file:   maroc_io.h
	new file:   message.txt
	new file:   pmt_scalers.c
	new file:   setup.txt
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Makefile 0 → 100644
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View file @ be5d40e5
#
# File:
# Makefile
#
# Description:
#
# $Date$
# $Rev$
#
CROSS_COMPILE =
CC = $(CROSS_COMPILE)g++
AR = ar
RANLIB = ranlib
CFLAGS = -O2 -fno-exceptions -fPIC -I/usr/include\
-I.
LINKLIBS = -lrt
PROGS = pmt_scalers
HEADERS = $(wildcard *.h)
SRC = ./pmt_scalers.c ./fpga_io.c ./maroc_io.c
OBJS = $(SRC:.C=.o)
all: $(PROGS) $(HEADERS)
clean distclean:
@rm -f $(PROGS) *~ *.o outlinkDef.{C,h}
%.o: %.C Makefile
@echo "Building $@"
$(CC) $(CFLAGS) \
-c $<
$(PROGS): $(OBJS) $(SRC) $(HEADERS) Makefile
@echo "Building $@"
$(CC) $(CFLAGS) -o $@ \
$(LINKLIBS) \
$(OBJS)
.PHONY: all clean distclean
fpga_io.c 0 → 100644
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#include <sys/socket.h>
#include <sys/types.h>
#include <netinet/in.h>
#include <netdb.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
#include <arpa/inet.h>
#include "fpga_io.h"
int sockfd_reg = 0;
int sockfd_event = 0;
typedef struct
{
int len;
int type;
int wrcnt;
int addr;
int flags;
int vals[1];
} write_struct;
typedef struct
{
int len;
int type;
int rdcnt;
int addr;
int flags;
} read_struct;
typedef struct
{
int len;
int type;
int rdcnt;
int data[1];
} read_rsp_struct;
void rich_write32(void *addr, int val)
{
write_struct ws;
ws.len = 16;
ws.type = 4;
ws.wrcnt = 1;
ws.addr = (int)((long)addr);
ws.flags = 0;
ws.vals[0] = val;
write(sockfd_reg, &ws, sizeof(ws));
}
unsigned int rich_read32(void *addr)
{
read_struct rs;
read_rsp_struct rs_rsp;
int len;
rs.len = 12;
rs.type = 3;
rs.rdcnt = 1;
rs.addr = (int)((long)addr);
rs.flags = 0;
write(sockfd_reg, &rs, sizeof(rs));
len = read(sockfd_reg, &rs_rsp, sizeof(rs_rsp));
if(len != sizeof(rs_rsp))
printf("Error in %s: socket read failed...\n", __FUNCTION__);
return rs_rsp.data[0];
}
void rich_read32_n(int n, void *addr, unsigned int *buf)
{
read_struct rs;
read_rsp_struct rs_rsp;
int len, i;
for(i = 0; i < n; i++)
{
rs.len = 12;
rs.type = 3;
rs.rdcnt = 1;
rs.addr = (int)((long)addr);
rs.flags = 0;
write(sockfd_reg, &rs, sizeof(rs));
}
for(i = 0; i < n; i++)
{
len = read(sockfd_reg, &rs_rsp, sizeof(rs_rsp));
if(len != sizeof(rs_rsp))
printf("Error in %s: socket read failed...\n", __FUNCTION__);
buf[i] = rs_rsp.data[0];
}
}
int open_socket(int port)
{
struct sockaddr_in serv_addr;
int sockfd = 0;
if((sockfd = socket(AF_INET, SOCK_STREAM, 0)) < 0)
{
printf("\n Error : Could not create socket \n");
exit(1);
}
memset(&serv_addr, '0', sizeof(serv_addr));
serv_addr.sin_family = AF_INET;
serv_addr.sin_port = htons(port);
if(inet_pton(AF_INET, FPGA_IP_ADDR, &serv_addr.sin_addr)<=0)
{
printf("\n inet_pton error occured\n");
exit(1);
}
if( connect(sockfd, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0)
{
printf("\n Error : Connect Failed \n");
exit(1);
}
return sockfd;
}
void open_register_socket()
{
int n, val;
sockfd_reg = open_socket(6102);
/* Send endian test header */
val = 0x12345678;
write(sockfd_reg, &val, 4);
val = 0;
n = read(sockfd_reg, &val, 4);
printf("n = %d, val = 0x%08X\n", n, val);
}
void open_event_socket()
{
sockfd_event = open_socket(6103);
}
void close_register_socket()
{
if(sockfd_reg)
{
close(sockfd_reg);
sockfd_reg = 0;
}
}
void close_event_socket()
{
if(sockfd_event)
{
close(sockfd_event);
sockfd_event = 0;
}
}
fpga_io.h 0 → 100644
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View file @ be5d40e5
#ifndef FPGA_IO_H
#define FPGA_IO_H
typedef struct
{
union
{
unsigned int val;
struct
{
unsigned int cmd_fsu : 1;
unsigned int cmd_ss : 1;
unsigned int cmd_fsb : 1;
unsigned int swb_buf_250f : 1;
unsigned int swb_buf_500f : 1;
unsigned int swb_buf_1p : 1;
unsigned int swb_buf_2p : 1;
unsigned int ONOFF_ss : 1;
unsigned int sw_ss_300f : 1;
unsigned int sw_ss_600f : 1;
unsigned int sw_ss_1200f : 1;
unsigned int EN_ADC : 1;
unsigned int H1H2_choice : 1;
unsigned int sw_fsu_20f : 1;
unsigned int sw_fsu_40f : 1;
unsigned int sw_fsu_25k : 1;
unsigned int sw_fsu_50k : 1;
unsigned int sw_fsu_100k : 1;
unsigned int sw_fsb1_50k : 1;
unsigned int sw_fsb1_100k : 1;
unsigned int sw_fsb1_100f : 1;
unsigned int sw_fsb1_50f : 1;
unsigned int cmd_fsb_fsu : 1;
unsigned int valid_dc_fs : 1;
unsigned int sw_fsb2_50k : 1;
unsigned int sw_fsb2_100k : 1;
unsigned int sw_fsb2_100f : 1;
unsigned int sw_fsb2_50f : 1;
unsigned int valid_dc_fsb2 : 1;
unsigned int ENb_tristate : 1;
unsigned int polar_discri : 1;
unsigned int inv_discriADC : 1;
} bits;
} Global0;
union
{
unsigned int val;
struct
{
unsigned int d1_d2 : 1;
unsigned int cmd_CK_mux : 1;
unsigned int ONOFF_otabg : 1;
unsigned int ONOFF_dac : 1;
unsigned int small_dac : 1;
unsigned int enb_outADC : 1;
unsigned int inv_startCmptGray : 1;
unsigned int ramp_8bit : 1;
unsigned int ramp_10bit : 1;
unsigned int Reserved0 : 23;
} bits;
} Global1;
union
{
unsigned int val;
struct
{
unsigned int DAC0 : 10;
unsigned int Reserved0 : 6;
unsigned int DAC1 : 10;
unsigned int Reserved1 : 6;
} bits;
} DAC;
unsigned int Reserved0;
union
{
unsigned int val;
struct
{
unsigned int Gain0 : 8;
unsigned int Sum0 : 1;
unsigned int CTest0 : 1;
unsigned int MaskOr0 : 2;
unsigned int Reserved0 : 4;
unsigned int Gain1 : 8;
unsigned int Sum1 : 1;
unsigned int CTest1 : 1;
unsigned int MaskOr1 : 2;
unsigned int Reserved1 : 4;
} bits;
} CH[32];
} MAROC_Regs;
typedef struct
{
unsigned int Ch0_31_Hold1;
unsigned int Ch32_63_Hold1;
unsigned int Ch0_31_Hold2;
unsigned int Ch32_63_Hold2;
} MAROC_DyRegs;
typedef struct
{
/* 0x0000-0x0003 */ unsigned int Ctrl;
/* 0x0004-0x0007 */ unsigned int Reserved0[(0x0008-0x0004)/4];
/* 0x0008-0x000B */ unsigned int SpiCtrl;
/* 0x000C-0x000F */ unsigned int SpiStatus;
/* 0x0010-0x00FF */ unsigned int Reserved1[(0x0100-0x0010)/4];
} RICH_clk;
typedef struct
{
/* 0x0000-0x0003 */ unsigned int SerCtrl;
/* 0x0004-0x0007 */ unsigned int SerStatus;
/* 0x0008-0x000B */ unsigned int DACAmplitude;
/* 0x000C-0x000F */ unsigned int Reserved0[(0x0010-0x000C)/4];
/* 0x0010-0x009F */ MAROC_Regs Regs;
/* 0x00A0-0x00AF */ MAROC_DyRegs DyRegs_WrAll;
/* 0x00B0-0x00DF */ MAROC_DyRegs DyRegs_Rd[3];
/* 0x00E0-0x00FF */ unsigned int Reserved1[(0x0100-0x00E0)/4];
} RICH_MAROC_Cfg;
typedef struct
{
/* 0x0000-0x000F */ unsigned int DisableCh[4];
/* 0x0010-0x0013 */ unsigned int HitOrMask0;
/* 0x0014-0x0017 */ unsigned int HitOrMask1;
/* 0x0018-0x00FF */ unsigned int Reserved0[(0x0100-0x0018)/4];
/* 0x0100-0x01FF */ unsigned int Scalers[64];
} RICH_Maroc_Proc;
typedef struct
{
/* 0x0000-0x0003 */ unsigned int AdcCtrl;
/* 0x0004-0x0007 */ unsigned int Reserved0[(0x0008-0x0004)/4];
/* 0x0008-0x000B */ unsigned int Hold1Delay;
/* 0x000C-0x000F */ unsigned int Hold2Delay;
/* 0x0010-0x00FF */ unsigned int Reserved1[(0x0100-0x0010)/4];
} RICH_MAROC_Adc;
typedef struct
{
/* 0x0000-0x0003 */ unsigned int Lookback;
/* 0x0004-0x0007 */ unsigned int WindowWidth;
/* 0x0008-0x000B */ unsigned int BlockCfg;
/* 0x000C-0x000F */ unsigned int Reserved0[(0x0010-0x000C)/4];
/* 0x0010-0x0013 */ unsigned int DeviceID;
/* 0x0014-0x0017 */ unsigned int TrigDelay;
/* 0x0018-0x0023 */ unsigned int Reserved1[(0x0024-0x0018)/4];
/* 0x0024-0x0027 */ unsigned int FifoWordCnt;
/* 0x0028-0x002B */ unsigned int FifoEventCnt;
/* 0x002C-0x007F */ unsigned int Reserved2[(0x0080-0x002C)/4];
/* 0x0080-0x0083 */ unsigned int FifoData;
/* 0x0084-0x00FF */ unsigned int Reserved3[(0x0100-0x0084)/4];
} RICH_EvtBuilder;
typedef struct
{
/* 0x0000-0x0003 */ unsigned int ErrCtrl;
/* 0x0004-0x0007 */ unsigned int ErrAddrL;
/* 0x0008-0x000B */ unsigned int ErrAddrH;
/* 0x000C-0x000F */ unsigned int Reserved0[(0x0010-0x000C)/4];
/* 0x0010-0x0013 */ unsigned int HeartBeatCnt;
/* 0x0014-0x0017 */ unsigned int InitializationCnt;
/* 0x0018-0x001B */ unsigned int ObservationCnt;
/* 0x001C-0x001F */ unsigned int CorrectionCnt;
/* 0x0020-0x0023 */ unsigned int ClassifactionCnt;
/* 0x0024-0x0027 */ unsigned int InjectionCnt;
/* 0x0028-0x002B */ unsigned int EssentialCnt;
/* 0x002C-0x002F */ unsigned int UncorrectableCnt;
/* 0x0030-0x0033 */ unsigned int RamAddr;
/* 0x0034-0x0037 */ unsigned int RamWrData;
/* 0x0038-0x003B */ unsigned int RamRdData;
/* 0x003C-0x003F */ unsigned int Reserved1[(0x0040-0x003C)/4];
/* 0x0040-0x0043 */ unsigned int RegData;
/* 0x0044-0x0047 */ unsigned int RegCtrl;
/* 0x0048-0x004F */ unsigned int Reserved2[(0x0050-0x0048)/4];
/* 0x0050-0x0053 */ unsigned int MonRd;
/* 0x0054-0x0057 */ unsigned int MonWr;
/* 0x0058-0x005B */ unsigned int MonStatus;
/* 0x005C-0x005F */ unsigned int Reserved3[(0x0060-0x005C)/4];
/* 0x0060-0x0063 */ unsigned int XAdcCtrl;
/* 0x0064-0x0067 */ unsigned int XAdcStatus;
/* 0x0068-0x006F */ unsigned int Reserved4[(0x0070-0x0068)/4];
/* 0x0070-0x0073 */ unsigned int FiberCtrl;
/* 0x0074-0x0077 */ unsigned int FiberStatus;
/* 0x0078-0x00FF */ unsigned int Reserved5[(0x0100-0x0078)/4];
} RICH_Testing;
// Mux signal selection for SD->*Src registers
#define SD_SRC_SEL_0 0
#define SD_SRC_SEL_1 1
#define SD_SRC_SEL_MAROC_OR 2
#define SD_SRC_SEL_INPUT_1 5
#define SD_SRC_SEL_INPUT_2 6
#define SD_SRC_SEL_INPUT_3 7
#define SD_SRC_SEL_MAROC_OR1_0 10
#define SD_SRC_SEL_MAROC_OR1_1 11
#define SD_SRC_SEL_MAROC_OR2_0 12
#define SD_SRC_SEL_MAROC_OR2_1 13
#define SD_SRC_SEL_MAROC_OR3_0 14
#define SD_SRC_SEL_MAROC_OR3_1 15
#define SD_SRC_SEL_PULSER_DLY0 18
#define SD_SRC_SEL_PULSER_DLY1 19
#define SD_SRC_SEL_PULSER_DLY2 20
#define SD_SRC_SEL_PULSER_DLY0_N 21
#define SD_SRC_SEL_PULSER_DLY1_N 22
#define SD_SRC_SEL_PULSER_DLY2_N 23
#define SD_SRC_SEL_BUSY 24
typedef struct
{
/* 0x0000-0x0007 */ unsigned int OutSrc[2];
/* 0x000C-0x0037 */ unsigned int Reserved0[(0x0038-0x0008)/4];
/* 0x0038-0x003B */ unsigned int CTestSrc;
/* 0x003C-0x003F */ unsigned int TrigSrc;
/* 0x0040-0x0043 */ unsigned int SyncSrc;
/* 0x0044-0x007F */ unsigned int Reserved1[(0x0080-0x0044)/4];
/* 0x0080-0x0083 */ unsigned int PulserPeriod;
/* 0x0084-0x0087 */ unsigned int PulserLowCycles;
/* 0x0088-0x008B */ unsigned int PulserNCycles;
/* 0x008C-0x008F */ unsigned int PulserStart;
/* 0x0090-0x0093 */ unsigned int PulserStatus;
/* 0x0094-0x0097 */ unsigned int PulserDelay;
/* 0x0098-0x00FF */ unsigned int Reserved2[(0x0100-0x0098)/4];
/* 0x0100-0x0103 */ unsigned int ScalerLatch;
/* 0x0104-0x0107 */ unsigned int Reserved3[(0x0108-0x0104)/4];
/* 0x0108-0x010B */ unsigned int Scaler_GClk125;
/* 0x010C-0x010F */ unsigned int Scaler_Sync;
/* 0x0110-0x0113 */ unsigned int Scaler_Trig;
/* 0x0114-0x011B */ unsigned int Scaler_Input[2];
/* 0x011C-0x011F */ unsigned int Reserved4[(0x0120-0x011C)/4];
/* 0x0120-0x0127 */ unsigned int Scaler_Output[2];
/* 0x0128-0x012B */ unsigned int Reserved5[(0x012C-0x0128)/4];
/* 0x012C-0x0137 */ unsigned int Scaler_Or0[3];
/* 0x0138-0x0143 */ unsigned int Scaler_Or1[3];
/* 0x0144-0x0147 */ unsigned int Scaler_Busy;
/* 0x0148-0x014B */ unsigned int Scaler_BusyCycles;
/* 0x014C-0x01FF */ unsigned int Reserved6[(0x0200-0x014C)/4];
} RICH_sd;
typedef struct
{
/* 0x0000-0x00FF */ RICH_clk Clk;
/* 0x0100-0x01FF */ RICH_MAROC_Cfg MAROC_Cfg;
/* 0x0200-0x03FF */ RICH_sd Sd;
/* 0x0400-0x04FF */ RICH_MAROC_Adc MAROC_Adc;
/* 0x0500-0x0FFF */ unsigned int Reserved0[(0x1000-0x0500)/4];
/* 0x1000-0x15FF */ RICH_Maroc_Proc MAROC_Proc[3];
/* 0x1600-0x1FFF */ unsigned int Reserved1[(0x2000-0x1600)/4];
/* 0x2000-0x20FF */ RICH_EvtBuilder EvtBuilder;
/* 0x2100-0x2FFF */ unsigned int Reserved2[(0x3000-0x2100)/4];
/* 0x3000-0x30FF */ RICH_Testing Testing;
} RICH_regs;
#define OK 0
#define ERROR -1
#define FLASH_CMD_WRPAGE 0x12
#define FLASH_CMD_RD 0x13
#define FLASH_CMD_GETSTATUS 0x05
#define FLASH_CMD_WREN 0x06
#define FLASH_CMD_GETID 0x9F
#define FLASH_CMD_ERASE64K 0xDC
#define FLASH_BYTE_LENGTH 32*1024*1024
#define FLASH_MFG_MICRON 0x20
#define FLASH_DEVID_N25Q256A 0xBB19
#define FPGA_IP_ADDR "192.168.1.10"
void rich_write32(void *addr, int val);
unsigned int rich_read32(void *addr);
void rich_read32_n(int n, void *addr, unsigned int *buf);
void open_register_socket();
void open_event_socket();
void close_register_socket();
void close_event_socket();
#endif
maroc_io.c 0 → 100644
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maroc_io.h 0 → 100644
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#ifndef MAROC_IO_H
#define MAROC_IO_H
#include "fpga_io.h"
#define MAROC_NUM 3
void rich_clear_regs();
MAROC_Regs rich_shift_regs(MAROC_Regs regs);
void rich_print_regs(MAROC_Regs regs);
void rich_init_regs(MAROC_Regs *regs, int thr);
void rich_clear_dynregs();
void rich_shift_dynregs(MAROC_DyRegs wr, MAROC_DyRegs *rd1, MAROC_DyRegs *rd2, MAROC_DyRegs *rd3);
void rich_print_dynregs(MAROC_DyRegs regs);
void rich_init_dynregs(MAROC_DyRegs *regs);
float rich_print_scaler(char *name, unsigned int scaler, float ref);
void rich_dump_scalers();
void rich_get_scalers(unsigned int scalers[192], int normalize);
void rich_set_pulser(float freq, float duty, int count);
void rich_enable_all_tdc_channels();
void rich_disable_all_tdc_channels();
void rich_enable_tdc_channel(int ch);
void rich_disable_tdc_channel(int ch);
void rich_setup_readout(int lookback, int window);
void rich_soft_reset();
void rich_fifo_status();
int rich_fifo_nwords();
void rich_fifo_read(int *buf, int nwords);
void rich_process_buf(int *buf, int nwords, FILE *f, int print);
void rich_setmask_fpga_or(int m0_0, int m0_1, int m1_0, int m1_1, int m2_0, int m2_1);
void rich_load_setup(char *filename);
extern RICH_regs *pRICH_regs;
extern int maroc_ch_to_pixel[64];
#endif
message.txt 0 → 100644
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From: Wenze Xi <wxi@jlab.org>
Sent: Wednesday, February 20, 2019 12:25:07 PM
To: Xie, Junqi
Subject: How to configure and use PMT FPGA IP address & example software
Hi, JunQI
The PC fiber network card should be given an IP address on the 192.168.1.0 subnet. I normally just use: 192.168.1.1
The PMT/FPGA card has the IP address 192.168.1.10 hardcoded into the firmware. You can ping the FPGA card if the PC is configured properly.
In Centos/RHEL systems you can setup the network card IP address by using the configuration file located here:
/etc/sysconfig/network-scripts
For example, if the interface is "eth0" then the configuration file would be ifcfg-eth0
You can setup the manually assigned IP address. For example, my ethernet card is eth1 and my ifcfg-eth1 file looks like this:
DEVICE=eth1
HWADDR=00:C0:F2:41:09:3A
TYPE=Ethernet
ONBOOT=yes
#NM_CONTROLLED=yes
BOOTPROTO=static
IPADDR=192.168.1.1
NETMASK=255.255.255.0
If the Centos is running X windows you can also setup the IP address in the GUI under network configuration. There's a plenty of online documentation/examples for setting this up if more info is needed.
Also, I attached the example configuration software for the FPGA module that runs on the PC. At some point I'll need to update this to demonstrate the TDC event readout mode.
Best
Wenze
pmt_scalers.c 0 → 100644
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#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <maroc_io.h>
#define MAROC_ADC_RESOLUTION_12b 11
#define MAROC_ADC_RESOLUTION_10b 9
#define MAROC_ADC_RESOLUTION_8b 7
#define MAROC_MASK_DISABLE 0x0
#define MAROC_MASK_2ASIC 0x5
#define MAROC_MASK_3ASIC 0x7
void SetupMAROC_ADC(unsigned char h1, unsigned char h2, int resolution, int maroc_mask)
{
rich_write32(&pRICH_regs->MAROC_Adc.Hold1Delay, h1);
rich_write32(&pRICH_regs->MAROC_Adc.Hold2Delay, h2);
rich_write32(&pRICH_regs->MAROC_Adc.AdcCtrl, (resolution<<4) | (maroc_mask<<1) | 0x1);
rich_write32(&pRICH_regs->MAROC_Adc.AdcCtrl, (resolution<<4) | (maroc_mask<<1));
}
int main(int argc, char *argv[])
{
unsigned int scalers[192];
unsigned int pixels[192];
int i,j;
open_register_socket();
rich_soft_reset();
rich_load_setup("setup.txt");
while(1)
{
rich_get_scalers(scalers, 1);
for(i=0;i<192;i++)
{
int asic=i/64;
int maroc_ch=i%64;
int pixel = asic*64+maroc_ch_to_pixel[maroc_ch];
pixels[pixel] = scalers[i];
}
for(i=0;i<8;i++)
{
for(j=0;j<24;j++)
{
int pmt = j/8;
int col = j%8;
int row = i;
printf("%7u",pixels[64*pmt+8*row+col]);
if(col==7 && pmt<2)
printf(" | ");
}
printf("\n");
}
printf("\n");
printf("\n");
sleep(1);
fflush(stdout);
}
close_register_socket();
return 0;
}
setup.txt 0 → 100644
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#[GAIN_ASIC] asic_number gain0 gain1 ... gain63
#
# asic_number: 0 to 2, for MAROC ASIC number
#
# gainx: 0 to 255, where 0 => GAIN=0, 64 => GAIN=1, 255 => GAIN=4
# 64 integers must be specified, which map to
# 0-> 63: MAROC ASIC x channels 0->63
#
[GAIN_ASIC] 0
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
[GAIN_ASIC] 1
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
[GAIN_ASIC] 2
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
64 64 64 64 64 64 64 64
#[THRESHOLD_ASIC] asic_number threshold
#
# asic_number: 0 to 2, for MAROC ASIC number
#
# threshold: 0 to 1023 disciminator theshold
# pedestal typical in the 180 to 200 range
# signal threshold typically ~250 to 500
[THRESHOLD_ASIC] 0 250
[THRESHOLD_ASIC] 1 250
[THRESHOLD_ASIC] 2 250
#[PULSER_FREQUENCY] frequncy
# Pulse injector frequency in Hz
# frequency: 0 to 1000000
[PULSER_FREQUENCY] 1000
#[PULSER_AMPLITUDE] amplitude
# amplitude: pulser amplitude
# 0 to 4095
[PULSER_AMPLITUDE] 1000
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