Update README.md

README.md

 # fe_fpgareadoutcard_template
-Template FPGA firmware project providing template for front-end board to optically interface to the SSP for operating in the Jlab DAQ system.
-
-For details on added a new peripherla:
-- See Firmware/Source/fpgareadoutcard/work/fpgareadoutcard.vhd bottom for some details
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-For details on creating a peripheral that can received fixed latency trigger/sync and build events:
-- See Firmware/Source/fpgareadoutcard/test1_per/*
-- A simulation/testbench example is provided in the Vivado project
-
-Vivado 2017.4 Project
-- Firmware/Projects/fpgareadoutcard_ssp/fpgareadoutcard_ssp.xpr
+Template FPGA firmware project providing template for front-end board to optically interface to the 1Gbps Ethernet (using a 1.25Gbps PCS/PMA interface)