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• common:detector
• u_omega:simulate
• single:simulate
• synchrotron:simulate
• dis:results
• tcs:results
• single:reconstruct
• single:analyze
• synchrotron:results
• dvcs:results
• summary
• u_omega:results
• tcs:compile
• single:compile
• dis:generate: [18, 275, 1000]
• common:setup
• tcs:simulate: [18, 275, s800]
• dvcs:compile
• dis:simulate: [18, 275, 1000]
• dvcs:simulate
• dis:simulate: [18, 275, 100]
• dis:compile
• u_omega:compile
• synchrotron:compile
• tcs:simulate: [10, 100, s100]
• dis:generate: [5, 41, 1]
• dis:generate: [10, 100, 1000]
• dis:generate: [5, 41, 100]
• dis:generate: [5, 41, 10]
• dis:generate: [18, 275, 10]
• dis:generate: [10, 100, 100]
• dis:generate: [10, 100, 1]
• dis:generate: [18, 275, 100]
• dis:generate: [10, 100, 10]
• dis:generate: [18, 275, 1]
• dis:simulate: [10, 100, 1000]
• dis:simulate: [18, 275, 1]
• dis:simulate: [18, 275, 10]
• dis:simulate: [5, 41, 1]
• dis:simulate: [5, 41, 10]
• dis:simulate: [5, 41, 100]
• dis:simulate: [10, 100, 1]
• dis:simulate: [10, 100, 10]
• dis:simulate: [10, 100, 100]
• tcs:simulate: [5, 41, s450]